Posted by Frank Hale on 1999-04-28
BRASIER Matthew G wrote: > > As a general rule I would implement it so that internal instructions take 1 clock cycle (those that act on registers only), instructions which act on 3 or more registers would probably take two cycles, and those that require access of external storage would take >=5 (depending whether a cache miss occurs) It is probably best to simulate that a cache miss occurs 5% to 2% of the time. > > hope this helps a bit > Thank you for your help! I really appreciate it! -- From: Frank Hale Email: frankhale@xxxxxxxx.xxx.xxx ICQ: 7205161 Website: http://www.franksstuff.com (DOWN FOR A WHILE)
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